1. Technical Field
The disclosure relates in general to a built-in self-test (BIST) circuit, and more particularly to a BIST circuit for a high speed I/O port.
2. Description of the Related Art
The transmission speed of memories is ever-increasing, with a speed of an I/O port of a double-data-rate (DDR) memory already reaching a level in GHz. Similarly, it is necessary that a speed level of an I/O port of a DDR memory controller requires a GHz level in order to match with the DDR memory.
FIG. 1 shows a circuit diagram of a conventional memory controller 100 with an I/O port 150. The memory controller 100 includes a core circuit 110 and the I/O port 150. The core circuit 110 includes a control unit 160, an N-to-1 output signal parallel-to-serial converter 120, an N-to-1 enable signal parallel-to-serial converter 130. The I/O port 150 includes an output driver 154, an I/O pad 156 and an input driver 152.
An operating speed of the control unit 160 in the core circuit 110 is lower than that of the I/O port 150. Hence, a parallel output signal Out_P of the control unit 160 is first converted to a serial output signal Out_S, followed by increasing a data speed of the serial output signal Out_S. The serial output signal Out_S with an increased data speed is then outputted to the I/O port 156. Meanwhile, the control unit 160 converts a parallel enable signal En_P to a serial enable signal En_S. The serial enable signal En_S with an increased data speed is then transmitted to the I/O port 150.
The N-to-1 output signal parallel-to-serial converter 120 and the N-to-1 enable signal parallel-to-serial converter 130 are structurally identical circuits. The N-to-1 output signal parallel-to-serial converter 120 receives a clock signal CLK and an N-bit parallel output signal Out_P, and outputs an N-bit serial output signal Out_S in a clock cycle. Similarly, the N-to-1 enable signal parallel-to-serial converter 130 receives the clock signal CLK and an N-bit parallel enable signal En_P, and outputs an N-bit serial enable signal En_S in a clock cycle. For example, N is 4, 8 or another number.
The output driver 154 of the I/O port 150 has an input terminal, and an enable terminal EN for receiving the serial output signal Out_S and serial enable signal En_S, respectively. By asserting the serial enable signal En_S, the output driver 154 transmits the serial output signal Out_S to the I/O pad 156. An input terminal of the input driver 152, connected to the I/O pad 156, then transmits the serial output signal Out_S into the memory controller 100.
When the serial enable signal En_S is at a high level, the I/O pad 156 is tri-stated. When the serial enable signal En_S is at a low level, the I/O pad 156 outputs the serial output signal Out_S. For example, the serial output signal Out_S is a data signal, a command signal or an address signal of the memory controller 100.
The I/O port 150 is a bi-directional I/O port capable of generating an output signal and receiving an input signal. When the I/O port 150 in FIG. 1 lacks the input driver 152, the I/O port 150 serves as a one-directional I/O port capable of only generating an output signal.
Conventionally, an integrated circuit is tested when a manufacturing process of the integrated circuit is complete. An integrated circuit manufacturer usually provides a test pattern to a tester, which then feeds the test pattern into the integrated circuit under test, and determines whether the integrated circuit is defective according to an output signal of an I/O port of the integrated circuit. An integrated circuit passing the test can naturally be delivered to a downstream manufacturer. Conversely, an integrated circuit that fails the test should be discarded.
In order to test an integrated circuit having an I/O port in a GHz level, a speed of a tester needs to be correspondingly increased to the GHz level. However, most of the testers have an operating speed of approximately 100 MHz, which is incapable of carrying out a high speed test for a high performance integrated circuit.